Senior DFT / ATPG Engineer (Contract)

Senior DFT / ATPG Engineer – Contract

California, USA | Contract | Engineering | Competitive Hourly Rate | Multiple Openings

IN SHORT: DFT, ATPG, SoC/ASIC, MBIST, RTL, semiconductor engineering, long-term contract, 100% on-site in California.

We are working with a leading global semiconductor company to recruit experienced Senior DFT / ATPG Engineers for multiple long-term contract opportunities in California.

Details

• Contract: Long-term contract

• Location: California, USA

• Working arrangement: 100% on-site

• Contract type: W2 or C2C

• Rate: Competitive hourly rate, dependent on experience

• Openings: Multiple positions

• Work authorisation: Valid US work authorisation required (OPT cannot be considered)

Skills & Experience

• Key technologies: DFT, ATPG, SoC/ASIC

• Essential experience: 5+ years in DFT and ATPG engineering

• Technical expertise: MBIST, IO testing, clock DFT and RTL

• Tools: Industry-standard DFT/ATPG EDA tools

About the Role

Our client is seeking experienced Senior DFT / ATPG Engineers to support complex semiconductor development programmes.

You will take ownership of Design for Test (DFT) implementation and Automatic Test Pattern Generation (ATPG) across advanced SoC/ASIC designs, working closely with design, verification and test teams.

This is an opportunity to contribute to high-performance semiconductor projects within a fast-paced engineering environment.

Key Responsibilities

• Implement and deliver DFT and ATPG solutions for complex SoC/ASIC designs.

• Generate, analyse and debug ATPG patterns.

• Design and implement MBIST architectures, including memory testing and diagnostics.

• Apply IO testing methodologies for interface and pin-level validation.

• Support clock DFT implementation and clock verification.

• Apply scan-based testing, controllability and observability principles.

• Work with industry-standard DFT/ATPG EDA tools.

• Collaborate with RTL, digital design and verification teams to resolve testability issues.

• Communicate technical progress, risks and findings to stakeholders.

Essential Skills & Experience

• Minimum 5 years' hands-on experience in DFT and ATPG for SoC or ASIC designs.

• Strong understanding of DFT fundamentals, including controllability, observability and scan-based testing.

• Proven expertise in ATPG pattern generation, analysis and debugging.

• Experience with MBIST, memory test architectures and diagnostics.

• Knowledge of IO testing methodologies and interface validation.

• Solid understanding of clock DFT and clock verification.

• Strong knowledge of digital design and RTL fundamentals.

• Hands-on experience with industry-standard DFT/ATPG EDA tools.

• Excellent analytical, problem-solving and communication skills.

• Ability to work effectively in fast-paced semiconductor engineering environments.

Engagement Details

• Multiple Senior DFT / ATPG Engineer contract positions available.

• Long-term engagement with a leading global semiconductor organisation.

• 100% on-site working in California.

• W2 or C2C contract arrangements considered.

• Competitive hourly rates based on experience.

• Candidates must have valid US work authorisation. OPT candidates cannot be considered.